1. Field of Invention
The present invention relates to a fabricating method of a thin film transistor array (TFT array). More particularly, the present invention relates to a fabricating method of a thin film transistor array (TFT array) having an enhanced storage capacitor.
2. Description of Related Art
The proliferation of multi-media systems in our society depends to a large extent on the progressive development of semiconductor devices and display devices. Display devices such as the cathode ray tube (CRT) have been used for quite some time due to its remarkable display quality, reliability and low cost. Although the conventional CRT has many advantages, but the design problem of the electron gun renders is heavy, bulky and energy wasting. Moreover, there is always some potential danger of hurting viewer's eyes due to its emission of some radiation. With big leaps in the techniques of manufacturing semiconductor devices and optic-electronics devices, high picture quality, slim, low power consumption and radiation-free displays such as the thin film transistor liquid crystal displays (TFT-LCD) have gradually become mainstream display products.
Generally, a color TFT-LCD includes a color filter (C/F), a TFT array and a liquid crystal layer disposed therebetween. The TFT array includes a plurality of thin film transistors, which is arranged in an area array and is driven by a plurality of scan lines and data lines. Each thin film transistor is disposed in a pixel area and is electrically connected to a corresponding pixel electrode formed by indium tin oxide (ITO), indium zinc oxide (IZO) or other transparent conductive materials. Each thin film transistor is used to drive the liquid crystal layer to show various gray levels. Furthermore, in a pixel of the conventional TFT array, a storage capacitor may be formed by a pixel electrode, the corresponding scan line and a dielectric layer (e.g. a gate insulator and/or a passivation layer) therebetween. Also, the storage capacitor can be formed by a pixel electrode, a common line and a dielectric layer therebetween to provide better picture quality. In the prior art, storage capacitor is classified into Metal-Insulator-Metal (MIM) type and Metal-Insulator-ITO (MII) type, which are described as follow.
FIG. 1 is a cross-sectional view of a conventional MIM type storage capacitor. Referring to FIG. 1, in a conventional pixel structure, a MIM type storage capacitor is coupled by a scan line (not shown) and an upper electrode 120 or is coupled by a common line 100 and an upper electrode 120. It should be noted that the common line 100 (or the scan line) and the upper electrode is electrical isolated by a gate insulator 110 therebetween in the MIM type storage capacitor. Therefore, capacitance of the MIM type storage capacitor relates to thickness of the gate insulator 110. In other words, the smaller the thickness of the gate insulator 110, the larger the capacitance Cst of the MIM type storage capacitor is. Furthermore, a pixel electrode 140 is electrically connected to the upper electrode 120 through a contact via 132 formed in a passivation layer 130.
FIG. 2 is a cross-sectional view of a conventional MII type storage capacitor. Referring to FIG. 2, in a conventional pixel structure, a MII type storage capacitor is coupled by a scan line (not shown) and a pixel electrode 230 or is coupled by a common line 200 and a pixel electrode 230. Compared with the MIM type storage capacitor, the common line 200 (or the scan line) and the pixel electrode 230 is electrical isolated by a gate insulator 210 and a passivation layer 220 therebetween in the MII type storage capacitor. Therefore, capacitance of the MII type storage capacitor relates to total thickness of the gate insulator 210 and the passivation layer 220. In other words, the smaller the total thickness of the gate insulator 210 and the passivation layer 220, the larger the capacitance Cst of the MIM type storage capacitor is.
In the conventional TFT array mentioned above, the thickness of the gate insulator 210 and/or passivation layer 220 must be reduced to obtain a larger capacitance Cst without lowering aperture ratio. However, the reliability of thin film transistors may be affected when the thickness of the gate insulator 210 and/or passivation layer 220 is reduced.